The purpose of this article is to study the possibilities of using ternary logic in digital devices by developing and synthesizing a two-bit ternary counter based on asynchronous ternary T-triggers. The author seeks to prove the effectiveness and feasibility of the transition from traditional binary logic to multivalued calculus systems, in particular ternary, by creating a workable hardware implementation capable of stable cyclic switching of logical states in a symmetric ternary number system. In this paper, we provide an analytical review of the current state of development of ternary logic, consider its advantages and disadvantages, and describe the problems of synthesizing logical functions in the ternary environment. Based on the existing approaches, a ternary asynchronous T-trigger was designed using bipolar threshold elements of multivalued logic (BETL), emitter repeaters, and current switches. The proposed architecture allows to realize switching between three logical states (-1, 0, +1) with a high level of reliability. Truth tables for both a separate trigger and a two-bit ternary counter operating on its basis have been developed. This counter covers nine states, which corresponds to the numbers from 0 to 8 in decimal. The paper also provides detailed block diagrams of both the trigger and the counter, which provide a visual representation of the logic of the device. As a result of the study, we have proved the operability of the proposed technical solution, its potential efficiency in comparison with binary analogs, as well as the prospects for further implementation in digital systems. The obtained results demonstrate the feasibility of using ternary logic to build compact and energy-efficient logic elements of a new generation. In further research, the author sees the need to develop synchronous ternary circuits, expand the bit capacity of counters, and model the operation of the proposed devices in CAD environments to ensure practical use in modern digital systems.

ternary logic, T-trigger, asynchronous counter, multivalued logic, multi-threshold element of multi-valued logic, digital circuit

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1. Lebedieva, V. V., & Hunchenko, Yu. O. (2016). Informatics, information systems and technologies. Review of ternary logic. In Informatics, information systems and technologies: Abstracts of the 13th All-Ukrainian Conference of Students and Young Scientists (Odesa, April 8, 2016) (pp. 61–63). Odesa [in Ukrainian].

2. Martynovych, L. Ya. (2022). Design and synthesis of ternary logic elements. Computer Systems and Information Technologies. International Scientific Journal of Khmelnytskyi National University, 4, 52–60 [in Ukrainian]. https://doi.org/10.31891/csit-2022-4-8

3. Hunchenko, Yu., Martynovych, L., Tykhonova, K., & Slutskyi, D. (2020). Concept of building ternary logic devices. In Proceedings of the 5th All-Ukrainian Scientific and Practical Conference “Perspective directions of modern electronics, information and computer systems” (Dnipro, November 25–27, 2020) (pp. 93–94). Dnipro [in Ukrainian].

4. Levchuk, V., Hunchenko, Yu., Kuznichenko, S., et al. (2018). Concept of building logical and arithmetic devices for multivalued logics. In Proceedings of the International Scientific and Practical Conference “Information technologies and computer modeling” (Ivano-Frankivsk, May 14–18, 2018) (pp. 216–219). Ivano-Frankivsk [in Ukrainian]. https://journal.comp-sc.if.ua/test/index.php/ITCM/article/view/428/220

5. Multi-threshold element of multi-valued logic: Patent 118735 Ukraine: IPC H03K19/00. No. u 2017 01717; filed 23.02.2017; published 28.08.2017, Bulletin No. 16 [in Ukrainian].

6. T-flip-flop guide – advantages and disadvantages, how it works, types. Distributor of electronic components: website. Retrieved April 19, 2025, from https://www.allelcoelec.com/blog/introduction-to-t- flip-flops-and-their-working-principles.html?srsltid=AfmBOoo3sSIrZT8AYtbHr- 2hHjkFp8vSnjPjXz60LpkEtEoGJaVgpjbo#t2

7. T-flip-flop. GeeksForGeeks: website. Retrieved April 19, 2025, from https://www.geeksforgeeks.org/t-flip-flop/

8. Ternary RS-flip-flop: Patent 149386 Ukraine: IPC H03K19/00. No. u 2021 04077; filed 13.07.2021; published 11.11.2021, Bulletin No. 45 [in Ukrainian].

9. Design counter for given sequence. GeeksForGeeks: website. Retrieved April 21, 2025, from https://www.geeksforgeeks.org/design-counter-given-sequence/

10. 2-bit counter. Deldsim: website. Retrieved April 21, 2025, from https://www.deldsim.com/study/material/42/2-bit-up-counter/.